The present invention generally relates to an electronic apparatus and, in particular, relates to one such electronic apparatus including multiple wafer scale assemblies.
Wafer scale assemblies, in general, are semiconductor devices that include a number of semiconductor chips mounted on a common substrate. In many instances the substrate is a semiconductor material about the size of a semiconductor wafer having electrical connections formed thereon. The electrically conductive patterns serve to interconnect the various semiconductor chips mounted on the substrate as well as to interconnect the semiconductor substrate with terminal pads used for external connections. The terminal pads are usually connected to a plurality of pins to allow external connection to the wafer scale assembly via a corresponding plug. To date, such assemblies have been individually packaged and interconnection between two or more such assemblies has been effected by pin to pin connections external to the packages thereof. Usually these connections are accomplished using conventional techniques such as, wire wrapping.
One complicating factor of wafer scale asemblies is the means and mechanisms utilized to dissipate heat generated by the multiple chip assemblies. The heat dissipated by wafer scale assemblies often increases as the physical size of each functional chip is reduced since, as the functional chip size is reduced, larger numbers of such chips can be mounted and interconnected on a single substrate.
As overall systems increase in complexity, the interconnection of two or more such wafer scale assemblies becomes very desireable to thereby form a single electronic apparatus. As commonly known, one advantage of wafer scale assemblies is the increased operating speeds thereof due to the close proximity of the individual functional chips. This advantage can be lost when two or more such assemblies are interconnected due primarily to the length of the wire interconnections therebetween. In addition, the overall thermal dissipation considerations of a multiple wafer scale assembly apparatus become rather complex if such an apparatus is to be housed in a single package.
Consequently, a multiple wafer scale assembly apparatus that reduces the interconnection lengths between individual ones of the assemblies and avoids many of the conventional complexities of heat dissipation is clearly desireable to advance the field of very high density semiconductor assemblies.